ssi_tx_fifo_0_empty |
SSI Transmit FIFO 0 empty bit |
ssi_tx_fifo_1_empty |
SSI Transmit FIFO 1 empty bit |
ssi_rx_fifo_0_full |
SSI Receive FIFO 0 full bit |
ssi_rx_fifo_1_full |
SSI Receive FIFO 1 full bit |
ssi_rls |
SSI Receive Last Time Slot bit |
ssi_tls |
SSI Transmit Last Time Slot bit |
ssi_rfs |
SSI Receive Frame Sync bit |
ssi_tfs |
SSI Transmit Frame Sync bit |
ssi_transmitter_underrun_0 |
SSI Transmitter underrun 0 bit |
ssi_transmitter_underrun_1 |
SSI Transmitter underrun 1 bit |
ssi_receiver_overrun_0 |
SSI Receiver overrun 0 bit |
ssi_receiver_overrun_1 |
SSI Receiver overrun 1 bit |
ssi_tx_data_reg_empty_0 |
SSI Transmit Data register empty 0 bit |
ssi_tx_data_reg_empty_1 |
SSI Transmit Data register empty 1 bit |
ssi_rx_data_ready_0 |
SSI Receive Data Ready 0 bit |
ssi_rx_data_ready_1 |
SSI Receive Data Ready 1 bit |
ssi_rx_tag_updated |
SSI Receive tag updated bit |
ssi_cmd_data_reg_updated |
SSI Command data register updated bit |
ssi_cmd_address_reg_updated |
SSI Command address register updated bit |
ssi_tx_interrupt_enable |
SSI Transmit interrupt enable bit |
ssi_tx_dma_interrupt_enable |
SSI Transmit DMA enable bit |
ssi_rx_interrupt_enable |
SSI Receive interrupt enable bit |
ssi_rx_dma_interrupt_enable |
SSI Receive DMA enable bit |
ssi_tx_frame_complete |
SSI Tx frame complete enable bit on MXC91221 & MXC91311 only |
ssi_rx_frame_complete |
SSI Rx frame complete on MXC91221 & MXC91311 only |