linux/drivers/mxc/ssi/ssi_types.h File Reference

This header file contains SSI types. More...


Enumerations

enum  fifo_nb {
  ssi_fifo_0 = 0,
  ssi_fifo_1 = 1
}
enum  idle_state {
  clock_idle_state_1 = 0,
  clock_idle_state_0 = 1
}
enum  mode_i2s {
  i2s_normal = 0,
  i2s_master = 1,
  i2s_slave = 2
}
enum  ssi_mod {
  SSI1 = 0,
  SSI2 = 1
}
enum  ssi_status_enable_mask {
  ssi_tx_fifo_0_empty = 0x00000001,
  ssi_tx_fifo_1_empty = 0x00000002,
  ssi_rx_fifo_0_full = 0x00000004,
  ssi_rx_fifo_1_full = 0x00000008,
  ssi_rls = 0x00000010,
  ssi_tls = 0x00000020,
  ssi_rfs = 0x00000040,
  ssi_tfs = 0x00000080,
  ssi_transmitter_underrun_0 = 0x00000100,
  ssi_transmitter_underrun_1 = 0x00000200,
  ssi_receiver_overrun_0 = 0x00000400,
  ssi_receiver_overrun_1 = 0x00000800,
  ssi_tx_data_reg_empty_0 = 0x00001000,
  ssi_tx_data_reg_empty_1 = 0x00002000,
  ssi_rx_data_ready_0 = 0x00004000,
  ssi_rx_data_ready_1 = 0x00008000,
  ssi_rx_tag_updated = 0x00010000,
  ssi_cmd_data_reg_updated = 0x00020000,
  ssi_cmd_address_reg_updated = 0x00040000,
  ssi_tx_interrupt_enable = 0x00080000,
  ssi_tx_dma_interrupt_enable = 0x00100000,
  ssi_rx_interrupt_enable = 0x00200000,
  ssi_rx_dma_interrupt_enable = 0x00400000,
  ssi_tx_frame_complete = 0x00800000,
  ssi_rx_frame_complete = 0x001000000
}
enum  ssi_tx_rx_clock_polarity {
  ssi_clock_on_rising_edge = 0,
  ssi_clock_on_falling_edge = 1
}
enum  ssi_tx_rx_direction {
  ssi_tx_rx_externally = 0,
  ssi_tx_rx_internally = 1
}
enum  ssi_tx_rx_early_frame_sync {
  ssi_frame_sync_first_bit = 0,
  ssi_frame_sync_one_bit_before = 1
}
enum  ssi_tx_rx_frame_sync_active {
  ssi_frame_sync_active_high = 0,
  ssi_frame_sync_active_low = 1
}
enum  ssi_tx_rx_frame_sync_length {
  ssi_frame_sync_one_word = 0,
  ssi_frame_sync_one_bit = 1
}
enum  ssi_tx_rx_shift_direction {
  ssi_msb_first = 0,
  ssi_lsb_first = 1
}
enum  ssi_wait_states {
  ssi_waitstates0 = 0x0,
  ssi_waitstates1 = 0x1,
  ssi_waitstates2 = 0x2,
  ssi_waitstates3 = 0x3
}
enum  ssi_word_length {
  ssi_2_bits = 0x0,
  ssi_4_bits = 0x1,
  ssi_6_bits = 0x2,
  ssi_8_bits = 0x3,
  ssi_10_bits = 0x4,
  ssi_12_bits = 0x5,
  ssi_14_bits = 0x6,
  ssi_16_bits = 0x7,
  ssi_18_bits = 0x8,
  ssi_20_bits = 0x9,
  ssi_22_bits = 0xA,
  ssi_24_bits = 0xB,
  ssi_26_bits = 0xC,
  ssi_28_bits = 0xD,
  ssi_30_bits = 0xE,
  ssi_32_bits = 0xF
}


Detailed Description

This header file contains SSI types.


Enumeration Type Documentation

enum fifo_nb

This enumeration describes the FIFO number.

Enumerator:
ssi_fifo_0  FIFO 0
ssi_fifo_1  FIFO 1

enum idle_state

This enumeration describes the clock idle state.

Enumerator:
clock_idle_state_1  Clock idle state is 1
clock_idle_state_0  Clock idle state is 0

enum mode_i2s

This enumeration describes I2S mode.

Enumerator:
i2s_normal  Normal mode
i2s_master  Master mode
i2s_slave  Slave mode

enum ssi_mod

This enumeration describes index for both SSI1 and SSI2 modules.

Enumerator:
SSI1  SSI1 index
SSI2  SSI2 index not present on MXC 91221 and MXC91311

This enumeration describes the status/enable bits for interrupt source of the SSI module.

Enumerator:
ssi_tx_fifo_0_empty  SSI Transmit FIFO 0 empty bit
ssi_tx_fifo_1_empty  SSI Transmit FIFO 1 empty bit
ssi_rx_fifo_0_full  SSI Receive FIFO 0 full bit
ssi_rx_fifo_1_full  SSI Receive FIFO 1 full bit
ssi_rls  SSI Receive Last Time Slot bit
ssi_tls  SSI Transmit Last Time Slot bit
ssi_rfs  SSI Receive Frame Sync bit
ssi_tfs  SSI Transmit Frame Sync bit
ssi_transmitter_underrun_0  SSI Transmitter underrun 0 bit
ssi_transmitter_underrun_1  SSI Transmitter underrun 1 bit
ssi_receiver_overrun_0  SSI Receiver overrun 0 bit
ssi_receiver_overrun_1  SSI Receiver overrun 1 bit
ssi_tx_data_reg_empty_0  SSI Transmit Data register empty 0 bit
ssi_tx_data_reg_empty_1  SSI Transmit Data register empty 1 bit
ssi_rx_data_ready_0  SSI Receive Data Ready 0 bit
ssi_rx_data_ready_1  SSI Receive Data Ready 1 bit
ssi_rx_tag_updated  SSI Receive tag updated bit
ssi_cmd_data_reg_updated  SSI Command data register updated bit
ssi_cmd_address_reg_updated  SSI Command address register updated bit
ssi_tx_interrupt_enable  SSI Transmit interrupt enable bit
ssi_tx_dma_interrupt_enable  SSI Transmit DMA enable bit
ssi_rx_interrupt_enable  SSI Receive interrupt enable bit
ssi_rx_dma_interrupt_enable  SSI Receive DMA enable bit
ssi_tx_frame_complete  SSI Tx frame complete enable bit on MXC91221 & MXC91311 only
ssi_rx_frame_complete  SSI Rx frame complete on MXC91221 & MXC91311 only

This enumeration describes the clock edge to clock in or clock out data.

Enumerator:
ssi_clock_on_rising_edge  Clock on rising edge
ssi_clock_on_falling_edge  Clock on falling edge

This enumeration describes the clock direction.

Enumerator:
ssi_tx_rx_externally  Clock is external
ssi_tx_rx_internally  Clock is generated internally

This enumeration describes the early frame sync behavior.

Enumerator:
ssi_frame_sync_first_bit  Frame Sync starts on the first data bit
ssi_frame_sync_one_bit_before  Frame Sync starts one bit before the first data bit

This enumeration describes the Frame Sync active value.

Enumerator:
ssi_frame_sync_active_high  Frame Sync is active when high
ssi_frame_sync_active_low  Frame Sync is active when low

This enumeration describes the Frame Sync active length.

Enumerator:
ssi_frame_sync_one_word  Frame Sync is active when high
ssi_frame_sync_one_bit  Frame Sync is active when low

This enumeration describes the Tx/Rx frame shift direction.

Enumerator:
ssi_msb_first  MSB first
ssi_lsb_first  LSB first

This enumeration describes the wait state number.

Enumerator:
ssi_waitstates0  0 wait state
ssi_waitstates1  1 wait state
ssi_waitstates2  2 wait states
ssi_waitstates3  3 wait states

This enumeration describes the word length.

Enumerator:
ssi_2_bits  2 bits long
ssi_4_bits  4 bits long
ssi_6_bits  6 bits long
ssi_8_bits  8 bits long
ssi_10_bits  10 bits long
ssi_12_bits  12 bits long
ssi_14_bits  14 bits long
ssi_16_bits  16 bits long
ssi_18_bits  18 bits long
ssi_20_bits  20 bits long
ssi_22_bits  22 bits long
ssi_24_bits  24 bits long
ssi_26_bits  26 bits long
ssi_28_bits  28 bits long
ssi_30_bits  30 bits long
ssi_32_bits  32 bits long

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