mt9v111_coreReg Struct Reference


Data Fields

u32 addressSelect
u32 columnStart
u32 windowHeight
u32 windowWidth
u32 horizontalBlanking
u32 verticalBlanking
u32 outputControl
u32 rowStart
u32 pixelClockSpeed
u32 restart
u32 reset
u32 zoomColStart
u32 zomRowStart
u32 digitalZoom
u32 readMode
u32 green1Gain
u32 testData
u32 chipEnable

Detailed Description

Mt9v111 Core Register structure.

Field Documentation

select address bank for Core Register 0x4

Image core Registers written by image flow processor

Starting Column

1 means zoom by 2

Gain Settings

Horizontal Blank time, in pixels

Register to control sensor output

pixel date rate

Readmode: aspects of the readout of the sensor

reset the sensor to the default mode

Abandon the readout of current frame

Starting Row

test mode

Vertical Blank time, in pixels

Window Height

Window Width

Row start in the Zoom mode

Column start in the Zoom mode

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