Defines | |
#define | SPBA_CPU_SSI 0x07 |
#define | MXC_SSI1STX0 0x00 |
#define | MXC_SSI2STX0 0x00 |
#define | SSI_ENABLE_SHIFT 0 |
#define | SSI_EARLY_FRAME_SYNC_SHIFT 0 |
#define | SSI_PRESCALER_MODULUS_SHIFT 0 |
#define | SSI_RX_FIFO_1_COUNT_SHIFT 28 |
#define | SSI_FRAME_SYN_RESET_SHIFT 0 |
#define | AC97_MODE_ENABLE_SHIFT 0 |
#define | SSI_TEST_MODE_SHIFT 15 |
#define AC97_MODE_ENABLE_SHIFT 0 |
SSI AC97 Control Register (SACNT) bit shift definitions
#define MXC_SSI1STX0 0x00 |
SSI1 registers offset
#define MXC_SSI2STX0 0x00 |
SSI2 registers offset
#define SPBA_CPU_SSI 0x07 |
This include to define bool type, false and true definitions.
#define SSI_EARLY_FRAME_SYNC_SHIFT 0 |
STCR & SRCR Registers bit shift definitions
#define SSI_ENABLE_SHIFT 0 |
SCR Register bit shift definitions
#define SSI_FRAME_SYN_RESET_SHIFT 0 |
SSI Option Register (SOR) bit shift definitions
#define SSI_PRESCALER_MODULUS_SHIFT 0 |
STCCR & SRCCR Registers bit shift definitions
#define SSI_RX_FIFO_1_COUNT_SHIFT 28 |
SFCSR Register bit shift definitions
#define SSI_TEST_MODE_SHIFT 15 |
SSI Test Register (STR) bit shift definitions
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