Defines | |
#define | UART1_HW_FLOW 1 |
#define | UART1_UCR4_CTSTL 16 |
#define | UART1_DMA_ENABLE 0 |
#define | UART1_DMA_RXBUFSIZE 1024 |
#define | UART1_UFCR_RXTL 16 |
#define | UART1_UFCR_TXTL 16 |
#define | UART1_MUX_INTS INTS_MUXED |
#define | UART1_INT1 MX25_INT_UART1 |
#define | UART1_INT2 (-1) |
#define | UART1_INT3 (-1) |
#define UART1_DMA_ENABLE 0 |
This is option to enable (set this option to 1) or disable DMA data transfer
#define UART1_DMA_RXBUFSIZE 1024 |
Specify the size of the DMA receive buffer. The minimum buffer size is 512 bytes. The buffer size should be a multiple of 256.
#define UART1_HW_FLOW 1 |
This option allows to choose either an interrupt-driven software controlled hardware flow control (set this option to 0) or hardware-driven hardware flow control (set this option to 1).
#define UART1_INT1 MX25_INT_UART1 |
This define specifies the transmitter interrupt number or the interrupt number of the ANDed interrupt in case the interrupts are muxed. There exists a define like this for each UART port.
#define UART1_INT2 (-1) |
This define specifies the receiver interrupt number. If the interrupts of the UART are muxed, then we specify here a dummy value -1. There exists a define like this for each UART port.
#define UART1_INT3 (-1) |
This specifies the master interrupt number. If the interrupts of the UART are muxed, then we specify here a dummy value of -1. There exists a define like this for each UART port.
#define UART1_MUX_INTS INTS_MUXED |
This define specifies whether the muxed ANDed interrupt line or the individual interrupts from the UART port is integrated with the ARM core. There exists a define like this for each UART port. Valid values that can be used are INTS_NOTMUXED or INTS_MUXED.
#define UART1_UCR4_CTSTL 16 |
This specifies the threshold at which the CTS pin is deasserted by the RXFIFO. Set this value in Decimal to anything from 0 to 32 for hardware-driven hardware flow control. Read the HW spec while specifying this value. When using interrupt-driven software controlled hardware flow control set this option to -1.
#define UART1_UFCR_RXTL 16 |
Specify the MXC UART's Receive Trigger Level. This controls the threshold at which a maskable interrupt is generated by the RxFIFO. Set this value in Decimal to anything from 0 to 32. Read the HW spec while specifying this value.
#define UART1_UFCR_TXTL 16 |
Specify the MXC UART's Transmit Trigger Level. This controls the threshold at which a maskable interrupt is generated by the TxFIFO. Set this value in Decimal to anything from 0 to 32. Read the HW spec while specifying this value.
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