SCM Interrupt Control Register definitions (SCM_INTERRUPT_CTRL)


Defines

#define SCM_INTERRUPT_CTRL_ZEROIZE_MEMORY   0x4
#define SCM_INTERRUPT_CTRL_CLEAR_INTERRUPT   0x2
#define SCM_INTERRUPT_CTRL_MASK_INTERRUPTS   0x1

Detailed Description

These are the bit definitions for the SCM_INTERRUPT_CTRL register.

Define Documentation

#define SCM_INTERRUPT_CTRL_CLEAR_INTERRUPT   0x2

Clear outstanding SCM interrupt

#define SCM_INTERRUPT_CTRL_MASK_INTERRUPTS   0x1

Inhibit SCM interrupts

#define SCM_INTERRUPT_CTRL_ZEROIZE_MEMORY   0x4

Clear SCM memory

footer
©  Freescale Semiconductor, Inc., 2007.  All rights reserved.
Freescale Confidential Proprietary
NDA Required
doxygen